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L9-Low Power Design Techniques-Part II, by Virendra Singh

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L21-Structural Description in VHDL, by Virendra Singh

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L4-Logical Effort-A Way of Designing Fast CMOS Circuits Continued, by Virendra Singh

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L22-Behavioral Description in VHDL, by Virendra Singh

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L11-Arithmetic Implementation Strategies for VLSI-Part II, by Virendra Singh

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L33-Introduction to VLSI Testing, by Virendra Singh

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L34-VLSI Test Basics-I, by Virendra Singh

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L8-Low Power Design Techniques, by Virendra Singh

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L7-Power Estimation and Control in CMOS VLSI Circuits Continued, by Virendra Singh

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L19-Introduction to VHDL, by Virendra Singh

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L40-VLSI Design Verification: An Introduction, by Virendra Singh

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L41-VLSI Design Verification: Equivalence/Model Checking, by Virendra Singh

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L1-Historical Perspective and Future Trends in CMOS VLSI Circuit and System Design, by Virendra Singh

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L20-Basic Components in VHDL, by Virendra Singh

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L10-Arithmetic Implementation Strategies for VLSI, by Virendra Singh

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L18-Managing Concurrency and Time in Hardware Description Languages, by Virendra Singh

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L3-Logical Effort-A Way of Designing Fast CMOS Circuits, by Virendra Singh

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L37-VLSI Testing: Design for Test (DFT), by Virendra Singh

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L24-FSM + Datapath (GCD Example), by Virendra Singh

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L13-Arithmetic Implementation Strategies for VLSI-Part IV, by Virendra Singh

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L28-Multicycle MMIPS – FSM, by Virendra Singh

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L14-Interconnect Aware Design: Impact of Scaling, Buffer Insertion and Inductive Peaking, by Virendra Singh

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L6-Power Estimation and Control in CMOS VLSI Circuits, by Virendra Singh

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L27-Multicycle MMIPS, by Virendra Singh

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L17-Introduction to Hardware Description Languages, by Virendra Singh

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L30-Netlist and System Partitioning, by Virendra Singh

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L5-Logical Effort-A Way of Designing Fast CMOS Circuits-Part III, by Virendra Singh

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L31-Timing Analysis in the Context of Physical Design Automation, by Virendra Singh

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L42-VLSI Design Verification: Model Checking, by Virendra Singh

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L15-Interconnect Aware Design: Low Swing and Current Mode Signaling, by Virendra Singh

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