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Compiler Transformations in High Level Synthesis: Loop Unrolling and Function Inlining, by Preeti Ranjan Panda

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Timing Analysis & Critical Paths, by Preeti Ranjan Panda

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VHDL: Modelling Timing-Events & Transactions, by Preeti Ranjan Panda

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Introduction to Logic Synthesis, by Preeti Ranjan Panda

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Two-Level Logic Optimisation, by Preeti Ranjan Panda

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VHDL: Introduction to Hardware Description Languages & VHDL Basics, by Preeti Ranjan Panda

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Multi-Level Logic Synthesis: Technology Mapping, by Preeti Ranjan Panda

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Introduction to Timing Analysis, by Preeti Ranjan Panda

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Memory Modelling & Compiler Transformation in High Level Synthesis: Common Sub-Expression Elimination & Loop Invariant Code Motion, by Preeti Ranjan Panda

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VHDL: Specifying Hardware Behaviour with Processes, by Preeti Ranjan Panda

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Force Directed Scheduling & Register Allocation, by Preeti Ranjan Panda

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Efficient Solution to Retiming & Introduction to Logic Synthesis, by Preeti Ranjan Panda

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Multi-Level Logic Optimisation, by Preeti Ranjan Panda

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Finite State Machine Synthesis: Identifyinh Common Cubes & Graph Embedding, by Preeti Ranjan Panda

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Finite State Machine Synthesis: Introduction to FSM Encoding, by Preeti Ranjan Panda

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Hardware Transformations & ASAP/ALAP Scheduling, by Preeti Ranjan Panda

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Binary Decision Diagrams, by Preeti Ranjan Panda

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VHDL: Specifying Structure, Test Benches, Parameterisation, & Libraries, by Preeti Ranjan Panda

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Animation (Contd.), by Prem K Kalra

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Fractals (Contd.), by Prem K Kalra

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Curves (Contd.), by Prem K Kalra

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Clipping, by Prem K Kalra

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Transformations, by Prem K Kalra

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Hidden Surface Elimination, by Prem K Kalra

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Assignment-I, by Prem K Kalra

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Rendering, by Prem K Kalra

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Ray Tracing, by Prem K Kalra

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3D Viewing (Contd.), by Prem K Kalra

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Surfaces (Contd.), by Prem K Kalra

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Raster Graphics, by Prem K Kalra

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